1. Field of the Invention
The present invention relates to buffer circuits and hold circuits using them, and particularly to an improvement for reducing the offset voltage between the input and output in a wide range of output current.
2. Description of the Background Art
Buffer circuits are often used in electronic circuits performing various signal processings using voltage signals. The object of the buffer circuits is to transfer a voltage signal as it is without amplification, and particularly it is to transfer the same voltage signal with a reduced impedance. Accordingly, the buffer circuit is often connected to the output of a voltage signal generating portion which is a circuit portion for generating a voltage signal when the voltage signal generating portion has a high output impedance.
When another circuit is directly connected to the output of a voltage signal generating portion having a high output impedance, the voltage signal may vary because of the effect of the input impedance of the connected circuit. Since the buffer circuit receives a voltage signal with a high input impedance and outputs the received voltage signal with a low output impedance without distorting the voltage signal, the above-mentioned problem can be solved by interposing it in the transmission path of the voltage signal between the voltage signal generating portion and the other circuit.
While the buffer circuits are constructed as negative feedback circuits using operational amplifiers in some applications, they may be constructed as a simple circuit as shown in FIG. 19 in other examples. The buffer circuit shown in FIG. 19 is advantageous for its simple structure. In this buffer circuit, a voltage signal received as an input signal is applied to the base electrode of a pnp-type transistor Q51 through an input signal line IN and a voltage signal as an output signal is outputted through an output signal line OUT connected to the connection between the emitter electrode of an npn-type transistor Q57 and a constant current source I2.
The transistor Q51 has its emitter electrode connected to the base electrode of the transistor Q57 and also to the higher-potential power-supply line VCC through a constant current source I1. The transistor Q51 has its collector electrode connected to the ground-potential power-supply line GND. The transistor Q57 has its emitter electrode connected to the ground-potential power-supply line GND through the constant current source I2 and its collector electrode connected to the higher-potential power-supply line VCC.
The constant current source I1 supplies an emitter current to the transistor Q51, so that the potential of the emitter electrode of the transistor Q51 is higher than the potential of its base electrode. The emitter-base voltage V.sub.EB corresponding to the potential difference between them is given by the equation 1 below. EQU V.sub.EB =kT/q.multidot.1n(Ic/Is) Eq.1
Where k is the Boltzmann's constant, T is the absolute temperature (K), q is the electron charge, Ic is the collector current, and Is is the saturation current peculiar to the transistor. According to the equation 1, the emitter-base voltage V.sub.EB is uniquely determined by the collector current Ic, but it does not vary largely even if the collector current Ic varies, for it is represented by the logarithm function of the collector current Ic.
In this operating state, the base current is smaller than the emitter current by the current amplification factor of the transistor because of the current amplifying action of the transistor. Since a lateral pnp-type transistor used in a semiconductor integrated circuit usually has a current amplification factor expressed in tens, a variation in the emitter current is attenuated by a factor of tens when it appears in the base current. The voltage variation is approximately equal between the base electrode and the emitter electrode since the emitter-base voltage V.sub.EB is approximately constant as shown above.
Accordingly, the ratio of the voltage variation to current variation of the emitter electrode, i.e. the impedance of the emitter electrode, is lower than the ratio of the voltage variation to current variation of the base electrode, i.e. than the impedance of the base electrode, approximately by the current amplification factor. That is to say, using the base electrode as the input and the emitter electrode as the output allows the circuit to receive the voltage signal with a high input impedance and output it with a low output impedance.
However, generally, the emitter-base voltage V.sub.EB of a transistor has a magnitude of about 0.6 to 0.7 V at room temperature. Accordingly, when a buffer circuit is formed by only a single stage of transistor, a voltage difference corresponding to the emitter-base voltage V.sub.EB occurs as an offset voltage between the input signal and the output signal, and then the buffer circuit cannot provide its function of transferring the voltage signal unchanged.
For the purpose of reducing the offset voltage, the buffer circuit of FIG. 19 includes the circuit part in the second stage (output stage) including the transistor Q57 as well as the circuit part in the first stage (input stage) including the transistor Q51. Then the emitter-base voltage V.sub.EB of the transistor Q51 is canceled by the emitter-base voltage V.sub.EB of the transistor Q57, and then the potential difference between the voltage signal input to the input signal line IN and the voltage signal output to the output signal line OUT, i.e. the offset voltage of the buffer circuit, can be reduced.
In the buffer circuit of FIG. 19, however, the two transistors are of different conductivity types: the transistor Q51 is pnp type and the transistor Q57 is npn type. It is not easy to set the emitter-base voltages V.sub.EB equal between transistors of different conductivity types. Particularly, it is further difficult to make the emitter-base voltages V.sub.EB of the two transistors coincide with each other in a wide range of output current to cancel the offset voltage, since the collector current of the transistor Q57 in the output stage varies in accordance with a variation in the current outputted through the output signal line OUT, i.e. a variation in the output current.